NASA announced on May 12 that its next-generation High Performance Spaceflight Computing (HPSC) processor is operating at 500 times the performance of the radiation-hardened chips currently flying in space, and delivers up to 100 times the computational capacity of present spaceflight computers. Testing of the palm-sized system-on-a-chip began at NASA's Jet Propulsion Laboratory in February and will continue for several months.
The processor was built by Microchip Technology Inc. of Chandler, Arizona, under a commercial partnership with JPL. "Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing," said Eugene Schwanbeck of NASA Langley Research Center. The project team marked the start of testing by symbolically sending an email titled "Hello Universe."
Once certified for flight, NASA plans to integrate HPSC into Earth orbiters, planetary rovers, deep-space probes and crewed habitats. The leap in onboard compute is meant to let spacecraft run AI models locally and react in real time to environments where signal round-trips to Earth make ground control impractical, a key building block for autonomous lunar and Martian missions.