At the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, Huawei introduced the "Tau (τ) Scaling Law," a proposed successor to Moore's Law. Instead of chasing ever-smaller transistors, it shifts the goal to cutting the signal-transmission time through a chip and the wider computing system.
The approach is built on a new 3D architecture Huawei calls "LogicFolding," which stacks logic, analog and memory circuits vertically rather than laying them out on a flat 2D grid. Huawei claims this delivers up to 55% higher transistor density and, by 2031, chips with density equivalent to a 1.4nm (14-angstrom) process — a way to bypass the EUV lithography it is barred from buying.
If the target holds, it would narrow China's manufacturing gap with the global frontier to about three years, down from today's five to seven. Huawei says it has already mass-produced 381 chips on the principle over six years, with its flagship Mate 90 / Kirin processors due later in 2026 set to be the first to ship the LogicFolding design.