{"data":{"id":1721,"lang":"en","title":"AMD Ramps 256-Core EPYC Venice on TSMC 2nm, the First HPC Chip on N2 With a 70% Performance Leap","summary":"AMD's 6th-gen EPYC Venice enters production on TSMC 2nm, the first HPC chip on N2, scaling to 256 Zen 6 cores with a claimed 70% performance gain.","category":"technology","category_label":"Technology","published_at":"2026-05-27T06:01:14Z","updated_at":"2026-05-27T06:01:14Z","url":"https://techtools.cz/tools/news/article/1721-amd-ramps-256-core-epyc-venice-on-tsmc-2nm-the-first-hpc-chip-on-n2-with-a-70","api_url":"https://techtools.cz/news-api/v1/articles/1721?lang=en","markdown_url":"https://techtools.cz/news-api/v1/articles/1721.md?lang=en","image_url":"https://cdn.mos.cms.futurecdn.net/4y3WTjM6BqyMGSzbKhXnSi.jpg","word_count":130,"reading_time_minutes":1,"sources":[{"url":"https://www.tomshardware.com/tech-industry/semiconductors/amd-begins-production-ramp-of-256-core-epyc-venice-on-tsmcs-2nm-node","domain":"tomshardware.com"},{"url":"https://www.amd.com/en/newsroom/press-releases/2026-5-20-amd-announces-production-ramp-of-next-generation-a.html","domain":"amd.com"}],"translation":{"lang":"cs","id":1794,"title":"AMD spustil výrobu 256jádrového EPYC Venice na 2nm od TSMC, prvního HPC čipu na N2 se 70% nárůstem výkonu","url":"https://techtools.cz/tools/news/clanek/1794-amd-spustil-vyrobu-256jadroveho-epyc-venice-na-2nm-od-tsmc-prvniho-hpc-cipu-na","api_url":"https://techtools.cz/news-api/v1/articles/1794?lang=cs"},"content":"AMD has begun production ramp of its 6th-generation EPYC server processor, codenamed Venice, on TSMC's 2nm (N2) process in Taiwan, making it the first high-performance computing chip in the industry to reach production on the new node. The Zen 6 design scales to 256 cores and delivers up to 1.6 TB/s of memory bandwidth.\n\nAMD claims Venice offers up to a 70% compute performance gain over the current EPYC Turin generation. Beyond Taiwan, the company plans to eventually manufacture the chip at TSMC's Arizona campus and has already teased a follow-on design, Verano, that integrates LPDDR memory for memory-hungry AI workloads.\n\nVenice anchors AMD's Helios rack-scale platform, which pairs the CPUs with Instinct MI450X GPUs and is on track for multi-gigawatt deployments starting in the second half of 2026."}}